The present invention relates generally to function generators and more specifically to an improved sin/cos generator.
To reduce the storage required on an integrated circuit for sin and cos generators, it has been suggested to use the law of signs with a small angle approximation shown in Table 1.
TABLE 1 ______________________________________ Sin (X + Y) = Sin X Cos Y + Sin Y Cos X .perspectiveto. Sin X + Y Cos X Cos (X + Y) = Cos X Cos Y - Sin X Sin Y .perspectiveto. Cos X - Y Sin X ______________________________________
Also the amount of value stored may be reduced by storing only one quadrant of values and complementing the values as illustrated in Table 2.
TABLE 2 __________________________________________________________________________ QUADRANT SIN (X + Y) COS (X + Y) SIN EQUATION COS EQUATION __________________________________________________________________________ Q1 Sin (X + Y) Cos (X + Y) Sin X + Y Cos X Cos X - Y Sin X Q2 Cos (X + Y) - Sin (X + Y) Cos X - Y Sin X - Sin X - Y Cos X Q3 - Sin (X + Y) - Cos (X + Y) - Sin X - Y Cos X - Cos X + Y Sin X Q4 - Cos (X + Y) Sin (X + Y) - Cos X + Y Sin X Sin X + Y Cos X __________________________________________________________________________
An implementation of this method is described in U.S. Pat. No. 4,486,846 to McCallister, et al. Four ROMs are provided and include a coarse sin ROM (sin x), a coarse cos ROM (cos X), fine sin ROM (Y sin X) and a fine cos ROM (Y cos X). Adders, multiplexers and control logic are used to combine these values to produce the sin and cos values for the appropriate quadrant. The negative values are produced by parallel inversion with an appropriate bias added. Although this implementation has substantially reduced the amount of the ROM storage required, further improvements in ROM capacity as well as error reduction are needed.
Thus it is an object of the present invention to provide an improved sin and cos generator of reduced ROM capacity and reduced errors.
These and other objects are achieved by storing values for sin X, cos X, and sin Y, multiplying the sin X and cos X by the value sin Y to produce partial products -sin Y sin X and sin Y cos X and adding partial products sin Y cos X to sin X to produce sin(X+Y) and adding the partial-products sin Y sin X to cos X to produce cos(X+Y). The values of sin X and cos X are stored for a sing quadrant without signed designation and quadrant control is provided to invert the appropriate values of sin X and cos X before adding and multiplying. A negative value is formed by generating the one's complement and adding a 1 in the least significant bit.
The multiplier uses a most significant bit portion of the sin X and cos X with sin Y to produce a plurality of partial products. A sin Y value decoder is provided to produce control values for the multiplier, which is a multiplexer, such as complemented, shifted and unshifted values of sin X or cos X and 0. The controls include a shift of 1 as well as a complement using recoding for bit pairs. The decoder is a storage device versus logic. The adder is a Wallace tree which produces sums and carries and a final adder is provided for adding the sum and carries of the Wallace tree. A 1 is also added in the adder in the appropriate bit position for rounding.
A first and second multiplexer each have their inputs connected to the sin and cos storage device and each of their outputs are connected to the multiplier and adder respectively. The multiplier includes first and second multipliers and a respective first and second adder to produce the sin and cos respectively. The first multiplexer has its output connected to the first adder and the second multiplier and the second multiplexer has its output connected to the second adder and the first multiplier. A single value of recoded value of sin Y is provided to both the first and second multipliers. Controllable inversion gates are provided at the output of the first and second multiplexer and the inverted output of the first multiplexer is connected to the input of the second multiplier such that the output of the first multiplexer Provided to the second multiplier is the inverse of the value that the first multiplexer provides to the first adder.